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1/27 preliminary data april 2003 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. M76DW52004TA m76dw52004ba 32mbit (4mb x8/ 2mb x16, dual bank, boot block) flash memory and 4mbit (256kb x16) sram, multiple memory product features summary multiple memory product ? 32 mbit (4mb x8 or 2mb x16), dual bank, boot block, flash memory ? 4 mbit (256kb x 16) sram supply voltage ?v ccf = 2.7v to 3.3v ?v ccs = 2.7v to 3.3v ?v ppf = 12v for fast program (optional) access time: 70, 90ns low power consumption electronic signature ? manufacturer code: 0020h ? top device code, M76DW52004TA: 225ch ? bottom device code, m76dw52004ba: 225dh flash memory programming time ? 10s per byte/word typical ? double word/ quadruple byte program memory blocks ? dual bank memory array: 16mbit+16mbit ? parameter blocks (top or bottom location) dual operations ? read in one bank while program or erase in other erase suspend and resume modes ? read and program another block during erase suspend unlock bypass program command ? faster production/batch programming v pp /wp pin for fast program and write protect temporary block unprotection mode common flash interface ? 64 bit security code figure 1. package extended memory block ? extra block used as security block or to store additional information 100,000 program/erase cycles per block sram 4 mbit (256kb x 16) access time: 70ns low v ccs data retention: 1.5v power down features using two chip enable inputs fbga lfbga73 (za) 8 x 11.6 mm
M76DW52004TA, m76dw52004ba 2/27 table of contents summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. lfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 address inputs (a0-a17). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 address inputs (a18-a20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data inputs/outputs (dq8-dq14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 data input/output or address input (dq15a?1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 flash chip enable (ef). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v pp/ write protect (v pp/ wp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 reset/block temporary unprotect (rpf).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ready/busy output (rb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 byte/word organization select (byte). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 sram chip enable (e1s, e2s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 sram upper byte enable (ubs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 sram lower byte enable (lbs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ccf supply voltage (2.7v to 3.3v). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v ccs supply voltage (2.7v to 3.3v).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 v ss ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. main operation modes, byte = vih(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 table 5. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. flash dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. sram dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. stacked lfbga73 8x11.6mm, 10x12 array, 0.8mm pitch, bottom view package outline14 table 8. stacked lfbga73 8x11.6mm, 10x12 array, 0.8mm pitch, package mechanical data. . . 15
3/27 M76DW52004TA, m76dw52004ba part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 9. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 flash device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 sram device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 sram summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. sram logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 sram operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 standby/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. sram read mode ac waveforms, address controlled . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. sram read ac waveforms, g controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. sram standby ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 10. sram read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12. sram write ac waveforms, w controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13. sram write ac waveforms, e1s controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. sram write ac waveforms, w controlled with g low. . . . . . . . . . . . . . . . . . . . . . 23 figure 15. sram write cycle waveform, ubs and lbs controlled, g low . . . . . . . . . . . . . . 23 table 11. sram write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 16. sram low v ccs data retention ac waveforms, e1 s or ub s / lb s controlled . . 25 table 12. sram low v ccs data retention characteristic. . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
M76DW52004TA, m76dw52004ba 4/27 summary description the M76DW52004TA/ba is a low voltage multiple memory product which combines two memory de- vices; a 32 mbit dual bank, boot block flash mem- ory (m29dw324d) and a 4 mbit sram. this document should be read in conjunction with the m29dw324d datasheet. recommended operating conditions do not allow both the flash and sram devices to be active at the same time. the memory is offered in an lfbga73 (8 x 11.6mm, 0.8 mm pitch) package and is sup- plied with all the bits erased (set to ?1?). figure 2. logic diagram table 1. signal names ai07581 21 a0-a20 e f v ccf M76DW52004TA m76dw52004ba g v ss w rp f e1 s e2 s ub s lb s v pp /wp v ccs dq0-dq14 15 dq15a?1 rb byte a0-a17 address inputs common to the flash and sram chips a18-a20 address inputs for flash chip only dq0-dq7 data inputs/outputs dq8-dq14 data inputs/outputs dq15a?1 data input/output or address input g output enable input w write enable input v ccf flash power supply v pp /wp v pp /write protect v ss ground v ccs sram power supply v sss sram ground nc not connected internally flash control functions e f chip enable input rp f reset/block temporary unprotect rb ready/busy output byte byte/word organization select sram control functions e1 s , e2 s chip enable inputs ub s upper byte enable input lb s lower byte enable input
5/27 M76DW52004TA, m76dw52004ba figure 3. lfbga connections (top view through package) ai07583 a 8 7 6 5 4 3 2 1 e b f a13 nc nc nc e2s dq12 rb a18 e f a4 nc nc dq4 dq15 /a-1 a9 a16 dq6 dq13 nc w a10 a5 nc v ss a17 rp f a14 v ccf e1 s nc g v ccs dq5 dq14 10 9 c dq10 dq11 a19 v pp /wp dq3 dq2 d dq8 dq9 lb s ub s dq1 dq0 g h a12 a11 a20 nc nc a8 a15 dq7 a2 a3 a6 a7 a0 nc nc nc a1 nc nc nc nc nc v ss j k m n nc nc byte nc
M76DW52004TA, m76dw52004ba 6/27 signal description see figure 2 logic diagram and table 1,signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a17). addresses a0-a17 are common inputs for the flash and the sram components. the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they con- trol the commands sent to the command interface of the internal state machine. the flash memory is accessed through the chip enable ( e f ) and write enable (w ) signals, while the sram is accessed through two chip enable signals (e1 s and e2 s ) and the write enable signal (w ). address inputs (a18-a20). addresses a18-a20 are inputs for the flash component only. the flash memory is accessed through the chip en- able (e f ) and write enable (w ) signals data inputs/outputs (dq0-dq7). the data i/o outputs the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the program/erase controller. data inputs/outputs (dq8-dq14). the data i/o outputs the data stored at the selected address during a bus read operation when byte is high, v ih . when byte is low, v il , these pins are not used and are high impedance. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. data input/output or address input (dq15a? 1). when byte is high, v ih , this pin behaves as a data input/output pin (as dq8-dq14). when byte is low, v il , this pin behaves as an address pin; dq15a?1 low will select the lsb of the ad- dressed word, dq15a?1 high will select the msb. throughout the text consider references to the data input/output to include this pin when byte is high and references to the address inputs to in- clude this pin when byte is low except when stated explicitly otherwise. flash chip enable (e f ). the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip en- able is at v il and rp f is at v ih the device is in ac- tive mode. when chip enable is at v ih the memory is deselected, the outputs are high imped- ance and the power consumption is reduced to the stand-by level. output enable (g ). the output enable, g , con- trols the bus read operation of the device. write enable (w ). the write enable, w , controls the bus write operation of the device. v pp/ write protect (v pp /wp ). the v pp /write protect pin provides two functions. the v pp func- tion allows the flash memory to use an external high voltage power supply to reduce the time re- quired for program operations. this is achieved by bypassing the unlock cycles and/or using the double word or quadruple byte program com- mands. the write protect function provides a hardware method of protecting the two outermost boot blocks in the flash memory. when v pp /write protect is low, v il , the memory protects the two outermost boot blocks; program and erase operations in these blocks are ignored while v pp /write protect is low, even when rp f is at v id . when v pp /write protect is high, v ih , the memory reverts to the previous protection status of the two outermost boot blocks. program and erase oper- ations can now modify the data in these blocks un- less the blocks are protected using block protection. when v pp /write protect is raised to v pp the mem- ory automatically enters the unlock bypass mode. when v pp /write protect returns to v ih or v il nor- mal operation resumes. during unlock bypass program operations the memory draws i pp from the pin to supply the programming circuits. see the m29dw324d datasheets for more details. reset/block temporary unprotect (rp f ). the reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been protected. note that if v pp /wp is at v il , then the two outer- most boot blocks will remain protected even if rp f is at v id . a hardware reset is achieved by holding reset/ block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see the m29dw324d datasheet for more details. holding rp f at v id will temporarily unprotect the protected blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . ready/busy output (rb ). the ready/busy pin is an open-drain output that can be used to identify when the flash memory is performing a program or erase operation. during program or erase op- erations ready/busy is low, v ol . ready/busy is high-impedance during read mode, auto select mode and erase suspend mode.
7/27 M76DW52004TA, m76dw52004ba after a hardware reset, bus read and bus write operations cannot begin until ready/busy be- comes high-impedance. byte/word organization select (byte ). the byte/word organization select pin is used to switch between the x8 and x16 bus modes of the flash memory. when byte/word organization se- lect is low, v il , the flash memory is in x8 mode, when it is high, v ih , the flash memory is in x16 mode. sram chip enable (e1 s , e2 s ). the chip en- able inputs activate the sram memory control logic, input buffers and decoders. e1 s at v ih or e2 s at v il deselects the memory and reduces the power consumption to the standby level. e1 s and e2 s can also be used to control writing to the sram memory array, while w remains at v il. it is not allowed to set e f at v il, e1 s at v il and e2 s at v ih at the same time. sram upper byte enable (ub s ). the upper byte enable enables the upper bytes for sram (dq8-dq15). ub s is active low. sram lower byte enable (lb s ). the lower byte enable enables the lower bytes for sram (dq0-dq7). lb s is active low. v ccf supply voltage (2.7v to 3.3v). v ccf pro- vides the power supply to the internal core of the flash memory device. it is the main power supply for all operations (read, program and erase). v ccs supply voltage (2.7v to 3.3v). v ccs pro- vides the power supply for the sram control pins. v ss ground. v ss is the ground reference for all voltage measurements in the flash and sram chips.
M76DW52004TA, m76dw52004ba 8/27 functional description the flash and sram components have separate power supplies. they are distinguished by three chip enable inputs: e f for the flash memory and, e1 s and e2 s for the sram. recommended operating conditions do not allow both the flash and the sram to be in active mode at the same time. the most common example is simultaneous read operations on the flash and the sram which would result in a data bus con- tention. therefore it is recommended to put the sram in the high impedance state when reading the flash and vice versa (see table 2 main oper- ation modes for details). figure 4. functional block diagram ai07582 flash memory 32 mbit (x16) e f g w rp f e1 s e2 s ub s lb s dq0-dq15/a-1 v ccf a18-a20 a0-a17 sram 4 mbit (x16) v ss v ccs v pp /wp rb byte
9/27 M76DW52004TA, m76dw52004ba table 2. main operation modes, byte = v ih (2) note: 1. x = don?t care = v il or v ih . 2. this table is also valid when byte = v il , with the only difference that dq15-dq8 are always high impedance in this case. 3. for the block protect and unprotect features, refer to the m29dw324d datasheet. only the in-system technique is available in the stacked product. 4. the read manufacturer code and read device code operations are not available in the stacked product (refer to the ??bus oper- ations? tables in m29dw324d datasheet for details). refer to the ?auto select command? in the m29dw324d to read the manu- facturer and device codes. operation mode e f rp f g w e1 s e2 s ub s lb s dq15-dq8 dq7-dq0 flash memory read v il v ih v il v ih sram must be disabled data output write v il v ih v ih v il sram must be disabled data input standby v ih v cc 0.3 x x any sram mode is allowed hi-z output disable x v ih v ih v ih any sram mode is allowed hi-z reset x v il x x any sram mode is allowed hi-z sram read flash must be disabled v il v ih v il v ih v il v il data out word read v il v ih v il v ih v il v ih data out hi-z v il v ih v il v ih v ih v il hi-z data out write flash must be disabled x v il v il v ih v il v il data in word write x v il v il v ih v ih v il data in hi-z x v il v il v ih v il v ih hi-z data in standby/ power down any flash mode is allowable xx v ih xx x hi-z xxxx v ih v ih hi-z xxx v il xx hi-z output disable any flash mode is allowable v ih v ih v il v ih v il v il hi-z v ih v ih v il v ih v il v ih hi-z v ih v ih v il v ih v ih v il hi-z
M76DW52004TA, m76dw52004ba 10/27 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not im- plied. exposure to absolute maximum rating con- ditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 3. absolute maximum ratings note: 1. depends on range. symbol parameter value unit min max t a ambient operating temperature (1) ?40 85 c t bias temperature under bias ?50 125 c t stg storage temperature ?65 150 c v io input or output voltage ?0.5 v ccf +0.3 v v ccf flash supply voltage ?0.6 4 v v ppf program voltage ?0.6 13.5 v v ccs sram supply voltage ?0.5 3.8 v
11/27 M76DW52004TA, m76dw52004ba dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 4, operating and ac measurement conditions. de- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. the operating and ac measurement parameters given in this section (see table 4 below) corre- spond to those of the stand-alone flash and sram devices. for compatibility purposes, the m29dw324d voltage range is restricted to v ccs in the stacked product. table 4. operating and ac measurement conditions figure 5. ac measurement i/o waveform figure 6. ac measurement load circuit table 5. device capacitance note: sampled only, not 100% tested. parameter sram flash memory units 70 70 90 min max min max min max v ccf supply voltage ? ? 3.0 3.6 2.7 3.6 v v ccs supply voltage 2.7 3.3 ? ? ? ? v ambient operating temperature ?40 85 ?40 85 ?40 85 c load capacitance (c l ) 30 30 30 pf input rise and fall times 3.3 10 10 ns input pulse voltages 0 to v ccf 0 to v ccf 0 to v ccf v input and output timing ref. voltages v ccf /2 v ccf /2 v ccf /2 v ai08186 v ccf 0v v ccf /2 ai08187 v ccf c l c l includes jig capacitance 25k ? device under test 0.1f v ccf 0.1f v pp 25k ? symbol parameter test condition typ max unit c in input capacitance v in = 0v, f=1 mhz 12 pf c out output capacitance v out = 0v, f=1 mhz 15 pf
M76DW52004TA, m76dw52004ba 12/27 table 6. flash dc characteristics note: 1. sampled only, not 100% tested. 2. in dual operations the supply current will be the sum of i cc1 (read) and i cc3 (program/erase). symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 (2) supply current (read) e f = v il , g = v ih , f = 6mhz 10 ma i cc2 supply current (standby) e f = v cc 0.2v, rp f = v cc 0.2v 100 a i cc3 (1,2) supply current (program/ erase) program/erase controller active v pp /wp = v il or v ih 20 ma v pp /wp = v pp 20 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7v cc v cc +0.3 v v pp voltage for v pp /wp program acceleration v cc = 3.0v 10% 11.5 12.5 v i pp current for v pp /wp program acceleration v cc = 3.0v 10% 15 ma v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = ?100 a v cc ?0.4 v v id identification voltage 11.5 12.5 v v lko program/erase lockout supply voltage 1.8 2.3 v
13/27 M76DW52004TA, m76dw52004ba table 7. sram dc characteristics note: 1. sampled only, not 100% tested. symbol parameter test condition min typ max unit i li input leakage current 0v v in v ccs 1 a i lo output leakage current 0v v out v ccs, sram outputs hi-z 1 a i ccs v cc standby current e1 s v ccs ? 0.2v v in v ccs ? 0.2v or v in 0.2v f = fmax (a0-a17 and dq0-dq15 only) f = 0 (g s , w s , ub s and lb s ) 715a e1 s v ccs ? 0.2v v in v ccs ? 0.2v or v in 0.2v, f = 0 715a i cc supply current f = fmax = 1/ avav , v ccs = 3.3v, i out = 0 ma 5.5 12 ma f = 1mhz, v ccs = 3.3v, i out = 0 ma 1.5 3 ma v il input low voltage ?0.3 0.8 v v ih input high voltage 2.2 v ccs +0.3 v v ol output low voltage v ccs = v cc min i ol = 2.1ma 0.4 v v oh output high voltage v ccs = v cc min i oh = ?1.0ma 2.4 v
M76DW52004TA, m76dw52004ba 14/27 package mechanical figure 7. stacked lfbga73 8x11.6mm, 10x12 array, 0.8mm pitch, bottom view package outline note: drawing is not to scale. bga-z50 ddd a2 a1 a sd fe e1 e ball "a1" se d1 d fd eb
15/27 M76DW52004TA, m76dw52004ba table 8. stacked lfbga73 8x11.6mm, 10x12 array, 0.8mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.400 0.0551 a1 0.250 0.0098 a2 0.910 0.0358 b 0.400 0.350 0.450 0.0157 0.0138 0.0177 d 8.000 7.900 8.100 0.3150 0.3110 0.3189 d1 7.200 0.2835 ddd 0.100 0.0039 e 11.600 11.500 11.700 0.4567 0.4528 0.4606 e1 8.800 0.3465 e 0.800 ? ? 0.0315 ? ? fd 0.400 0.0157 fe 1.400 0.0551 sd 0.400 ? ? 0.0157 ? ? se 0.400 ? ? 0.0157 ? ?
M76DW52004TA, m76dw52004ba 16/27 part numbering table 9. ordering information scheme devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the stmicroelectronics sales office nearest to you. example: m76 d w 5 2 0 0 4t a70zt device type m76 = mmp (flash + sram) architecture d = dual operation operating voltage w = v ccf = v ccs = 2.7v to 3.3v flash device size (die1 density) 5 = 32 mbit sram device size (die2 density) 2 = 4 mbit die3 0 = die3 density die4 0 = die4 density flash specification details 4t = 1/2 & 1/2 partitioning, top boot block 4b = 1/2 & 1/2 partitioning, bottom boot block stacked specification details a = 0.15m flash & sram speed 70 = 70ns 90 = 90ns package and temperature range z = lfbga73: 8 x 11.6mm, 0.8mm pitch option t = tape & reel packing
17/27 M76DW52004TA, m76dw52004ba flash device the M76DW52004TA/ba contains one 32 mbit flash memory. for detailed information on how to use the flash memory refer to the m29dw324d datasheet, which is available on the stmicroelec- tronics web site, www.st.com. sram device sram summary description the sram is a 4mbit asynchronous random ac- cess memory which features a super low voltage operation and low current consumption with an ac- cess time of 70ns under all conditions. the mem- ory operations can be performed using a single low voltage supply, 2.7v to 3.3v, which is the same as the flash voltage supply. figure 8. sram logic diagram data in drivers 256kb x 16 ram array 2048 x 2048 column decoder row decoder a0-a10 w s ub s lb s sense amps a11-a17 power-down circuit dq0-dq7 dq8-dq15 g s ub s lb s ai 07939 e1 s e2 s
M76DW52004TA, m76dw52004ba 18/27 sram operations there are five standard operations that control the sram component. these are bus read, bus write, standby/power-down, data retention and output disable. a summary is shown in table 2, main operation modes read. read operations are used to output the contents of the sram array. the sram is in read mode whenever write enable, w s , is at v ih , out- put enable, g s , is at v il , chip enable, e1 s , is at v il , chip enable, e2 s , is at v ih , and byte enable inputs, ub s and lb s are at v il . valid data will be available on the output pins after a time of t avqv after the last stable address. if the chip enable or output enable access times are not met, data access will be measured from the limiting parameter (t e1lqv , t e2hqv , or t glqv ) rath- er than the address. data out may be indetermi- nate at t e1lqx , t e2hqx and t glqx , but data lines will always be valid at t avqv (see table 10, table 10, figures 9 and 10, sram read ac character- istics). write. write operations are used to write data to the sram. the sram is in write mode whenever w and e1 s are at v il , and e2 s is at v ih . either the chip enable inputs, e1 s and e2 s , or the write en- able input, w s , must be deasserted during ad- dress transitions for subsequent write cycles. a write operation is initiated when e1 s is at v il , e2 s is at v ih and w is at v il . the data is latched on the falling edge of e1 s , the rising edge of e2 s or the falling edge of w s , whichever occurs last. the write cycle is terminated on the rising edge of e1 s , the rising edge of w or the falling edge of e2 s , whichever occurs first. if the output is enabled (e1 s =v il , e2 s =v ih and g s =v il ), then w will return the outputs to high im- pedance within t wlqz of its falling edge. care must be taken to avoid bus contention in this type of op- eration. the data input must be valid for t dvwh be- fore the rising edge of write enable, for t dve1h before the rising edge of e1 s or for t dve2l before the falling edge of e2 s , whichever occurs first, and remain valid for t whdx , t e1hax or t e2lax (see table 11, sram write ac characteristics, figures 12, 13, 14 and 15). standby/power-down. the sram component has a chip enabled power-down feature which in- vokes an automatic standby mode (see table 10, sram read ac characteristics, figure 11, sram standby ac waveforms). the sram is in standby mode whenever either chip enable is deasserted, e1 s at v ih or e2 s at v il . it is also possible when ub s and lb s are at v ih . data retention. the sram data retention per- formance as v ccs goes down to v dr are de- scribed in table 12, sram low v ccs data retention characteristic, and figure 16, sram low v ccs data retention ac waveforms, e1 s or ub s / lb s controlled. in e1 s controlled data reten- tion mode, the minimum standby current mode is entered when e1 s v ccs ? 0.2v and e2 s 0.2v or e2 s v ccs ? 0.2v. in e2 s controlled data re- tention mode, minimum standby current mode is entered when e2 s 0.2v. output disable. the data outputs are high im- pedance when the output enable, g s , is at v ih with write enable, w s , at v ih .
19/27 M76DW52004TA, m76dw52004ba figure 9. sram read mode ac waveforms, address controlled note: e1 s = low, e2 s = high, g = low, ub s and/or lb s = high, w = high. figure 10. sram read ac waveforms, g controlled note: write enable (w ) = high. address valid prior to or at the same time as e1 s , ub s and lb s going low. figure 11. sram standby ac waveforms ai07942 tavav tavqv taxqx a0-a17 dq0-dq15 valid data valid data valid ai07943b tavav te1lqv te1hqz tglqv tglqx tghqz data valid a0-a17 e1 s g dq0-dq15 te2hqv valid te2lqz e2 s tblqv tblqx tbhqz ub s , lb s te1lqx te2hqx ai07913b tpd e2 s i cc tpu 50% e1 s
M76DW52004TA, m76dw52004ba 20/27 table 10. sram read ac characteristics note: 1. sampled only. not 100% tested. symbol alt parameter sram unit min max t avav t rc read cycle time 70 ns t av qv t acc address valid to output valid 70 ns t axqx t oh address transition to output transition 10 ns t bhqz t bhz ub s , lb s disable to hi-z output 25 ns t blqv t ab ub s , lb s access time 70 ns t blqx t blz ub s , lb s enable to low-z output 5ns t e1lqv t e2hqv t acs1 chip enable 1 low or chip enable 2 high to output valid 70 ns t e1lqx t e2hqx t clz1 chip enable 1 low or chip enable 2 high to output transition 10 ns t e1hqz t e2lqz t hzce chip enable high or chip enable 2 low to output hi-z 25 ns t ghqz t ohz output enable high to output hi-z 25 ns t glqv t oe output enable low to output valid 35 ns t glqx t olz output enable low to output transition 5 ns t pd (1) chip enable 1 high or chip enable 2 low to power down 70 ns t pu (1) chip enable 1 low or chip enable 2 high to power up 0 ns
21/27 M76DW52004TA, m76dw52004ba figure 12. sram write ac waveforms, w controlled note: 1. w , e1 s , e2 s , ub s and/or lb s must be asserted to initiate a write cycle. output enable (g ) = low (otherwise, dq0-dq15 are high impedance). if e1 s , e2 s and w are deasserted at the same time, dq0-dq15 remain high impedance. 2. the i/o pins are in output mode and input signals must not be applied. ai07944b tavav twhax tdvwh input valid a0-a17 e1 s w dq0-dq15 valid e2 s tavwh tblwh tghqz twhdz tavwl ub s , lb s te2hwh te1lwh g twlwh note 2
M76DW52004TA, m76dw52004ba 22/27 figure 13. sram write ac waveforms, e1 s controlled note: 1. w s , e1 s , e2 s , ub s and/or lb s must be asserted to initiate a write cycle. output enable (g s ) = low (otherwise, dq0-dq15 are high impedance). if e1 s , e2 s and w are deasserted at the same time, dq0-dq15 remain high impedance. 2. if e1 s , e2 s and w are deasserted at the same time, dq0-dq15 remain high impedance. 3. the i/o pins are in output mode and input signals must not be applied. ai07945b tavav te1hax tdve1h tdve2l input valid a0-a17 e1 s w dq0-dq15 valid e2 s tave1h tave2l tble1h tble2l tghqz te1hdz te2ldz tave1l ub s , lb s te2he2l te1le1h g twle1h twle2l tave2h te2lax note 3
23/27 M76DW52004TA, m76dw52004ba figure 14. sram write ac waveforms, w controlled with g low note: 1. if e1 s , e2 s and w are deasserted at the same time, dq0-dq15 remain high impedance. figure 15. sram write cycle waveform, ub s and lb s controlled, g low note: 1. if e1 s , e2 s and w are deasserted at the same time, dq0-dq15 remain high impedance. ai07946b tavav twhax tdvwh input valid a0-a17 e1 s w dq0-dq15 valid e2 s tavwh twlwh tavwl twhdz twhqx tblwh ub s , lb s te1lwh te2hwh twlqz ai07947b tavav tbhax tdvbh input valid a0-a17 e1 s w dq0-dq15 valid e2 s tavbh twlbh tavbl tbhdz tblbh ub s , lb s te1lbh te2hbh
M76DW52004TA, m76dw52004ba 24/27 table 11. sram write ac characteristics symbol alt parameter sram unit min max t avav t wc write cycle time 70 ns t av e1l , t ave 2h , t avwl, t avbl t as address valid to beginning of write 0 ns t ave 1h , t ave2l t aw address valid to chip enable 1 low or chip enable 2 high 60 ns t av wh t aw address valid to write enable high 60 ns t blwh t ble1h t ble2l t av bh t bw ub s , lb s valid to end of write 60 ns t blbh t bw ub s , lb s low to ub s , lb s high 60 ns t dve1h , t dve2l , t dvwh t dvbh t dw input valid to end of write 30 ns t e1hax , t e2lax , t whax t bhax t wr end of write to address change 0 ns t e1hdz , t e2ldz , t whdz t bhdz t hd address transition to end of write 0 ns t e1le1h , t e1lbh t e1lwh t cw1 chip enable 1 low to end of write 60 ns t e2he2l, t e2hbh, t e2hwh t cw2 chip enable 2 high to end of write 60 ns t ghqz t ghz output enable high to output hi-z 25 ns t whqx t dh write enable high to input transition 5 ns t wlbh t wp write enable low to ub s , lb s high 50 ns t wlqz t whz write enable low to output hi-z 25 ns t wlwh t wle1h t wle2l t wp write enable pulse width 50 ns
25/27 M76DW52004TA, m76dw52004ba figure 16. sram low v ccs data retention ac waveforms, e1 s or ub s / lb s controlled table 12. sram low v ccs data retention characteristic 2. sampled only. not 100% tested. symbol parameter test condition min typ max unit i ccdr supply current (data retention) v ccs = 1.5v, e1 s v ccs ? 0.2v, v in v ccs ? 0.2v or v in 0.2v 310a v dr supply voltage (data retention) 1.5 3.3 v t cdr chip disable to power down 0 ns t r operation recovery time 70 ns ai07918b e1 s or ub s , lb s tcdr v ccs tr data retention mode v ccs (min) v ccs (min)
M76DW52004TA, m76dw52004ba 26/27 revision history table 13. document revision history date version revision details 11-apr-2003 1.0 first issue
27/27 M76DW52004TA, m76dw52004ba information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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